MINISTRY OF ELECTRONICS AND INFORMATION TECHNOLOGY
(R&D in Electronics Group)
Notification No. EE-9/5/2021-R&D-E.
New Delhi, the 21st December, 2021
Subject : Design Linked Incentive (DLI) Scheme
1. Background
1.1 The electronics industry is the world’s largest and fastest growing industry with applications in all sectors of the economy. Semiconductors have been a key enabler in the advancement of electronics for over five decades and will play an even greater role with the emergence of new applications including IoT, artificial intelligence, 5G, smart mobility, robotics, etc.
1.2 The global semiconductor market stood at ~$466B (₹35 lakh crore) in 2020 and is expected to grow to ~$656B (₹49 lakh crore) by 2025. The semiconductor industry has steadily evolved to create various business models, starting from fully integrated design manufacturers (IDMs) to tool manufacturers, EDA companies, foundries, and semiconductor design companies. Today, few companies operate as IDMs and most players have restricted operations to core competencies. While semiconductor design companies are solely focussed on product design and development, foundries offer semiconductor manufacturing services.
1.3 With an exceptional talent pool of 20% of world’s semiconductor design engineers, India remains a highly attractive destination for global semiconductor design companies. Thousands of chips are designed every year in India by these engineers. Despite a thriving design ecosystem and availability of trained and highly competent manpower, a minuscule portion of the Intellectual Property (IP) generated belongs to the country as it is mostly held by the global companies. Moreover, the domestic semiconductor design ecosystem is still in a nascent stage with the cumulative annual revenue of domestic semiconductor design companies estimated to be less than ₹150 Crore. There is near absence of design-houses for electronic products such as mobile phones, IT hardware, smart meters, set-top boxes, hearables and wearables, infotainment products, IoT devices, and other communication devices.
1.4 The total electronic design market in India, estimated at ₹35000 Crore in 2020 and growing at a CAGR of ~15.4%, necessitates fostering the domestic semiconductor design industry to not only meet the domestic requirement and service global customers but also achieve self-reliance and mitigate the security concerns of this strategic sector.
1.5 The National Policy on Electronics (NPE 2019) aims to position India as a global hub for Electronics System Design and Manufacturing (ESDM) by encouraging and driving capabilities in the country for developing core components, including chipsets, and creating an enabling environment for the industry to compete globally. The NPE 2019 also envisions the creation of a vibrant and dynamic semiconductor design ecosystem in the country by way of incentivizing the startups and making design infrastructure accessible to them.
1.6 Government has been working to create a conducive environment for design and manufacturing of electronics and offer incentives comparable with those offered in competing economies. While several existing schemes are effectively contributing towards various segments of electronics manufacturing (including electronic devices, components & semiconductors), no specific policy thrust, or interventions have been done for semiconductor design companies till date. The need to achieve self-reliance and aim for technology leadership in semiconductor design necessitates multi-fold growth in the Indian semiconductor design industry by way of providing financial incentives and infrastructural support to offset entry barriers and disabilities.
2. Objectives: The Design Linked Incentive (DLI) Scheme shall offer financial incentives as well as design infrastructure support across various stages of development and deployment of semiconductor design for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design over a period of 5 years with the objectives of:
2.1 Nurturing 100 domestic companies of semiconductor design for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design and facilitating the growth of not less than 20 such companies to achieve turnover of more than ₹1500 Crore in the next 5 years.
2.2 Achieving significant indigenization in semiconductor and electronic products and IPs deployed in the country, thereby facilitating import substitution and value addition in electronics sector in the next 5 years.
2.3 Strengthening the design infrastructure through incubators for semiconductor design and facilitating access to startups and MSMEs.
3. Eligibility: Financial incentives and design infrastructure support will be extended to domestic companies, startups and MSMEs engaged in semiconductor design for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design under the DLI Scheme.
3.1 Domestic companies shall be defined as those which are owned by resident Indian citizens as defined in the FDI Policy Circular of 2017 or extant norms. A company is considered as ‘Owned’ by resident Indian citizens if more than 50% of the capital in it is beneficially owned by resident Indian citizens and/or Indian companies, which are ultimately owned and controlled by resident Indian citizens.
3.2 MSMEs shall be defined as per the Gazette Notification by Ministry of Micro, Small and Medium Enterprises, dated 1st June 2020 or extant norms.
3.3 Startups shall be defined as per the DPIIT notification dated 19th February 2019 or extant norms.
3.4 The approved applicants that claim incentives under the scheme shall retain their domestic status (i.e. more than 50% of the capital in it is beneficially owned by resident Indian citizens and/or Indian companies, which are ultimately owned and controlled by resident Indian citizens) for a period of three years after claiming incentives under the scheme.
3.5 Eligibility under DLI Scheme shall not affect eligibility under any other Scheme and vice-versa.
4. Tenure: Applications under the Scheme will be initially open for three (3) years from 01.01.2022. The applications received under the Scheme will be appraised on an ongoing basis and implementation will continue as per the approvals accorded under the Scheme.
5. Incentives under the Scheme: Financial incentives shall be provided to approved applicants under the Scheme in the following manner
5.1 Product Design Linked Incentive – Reimbursement of up to 50% of the eligible expenditure subject to a ceiling of ₹15 Crore per application will be provided as fiscal support to the approved applicants who are engaged in semiconductor design for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design. The applicants should submit their proposals for development of semiconductor design for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design that can be demonstrated in an operational environment and are ready for volume production.
5.2 Deployment Linked Incentive – Incentive of 6% to 4% of net sales turnover over 5 years subject to a ceiling of ₹30 Crore per application will be provided to approved applicants whose semiconductor design for Integrated Circuits (ICs), Chipsets, System on Chips (SoCs), Systems & IP Cores and semiconductor linked design are deployed in electronic products.
5.3 The detailed breakup of the support under the DLI Scheme is at Annexure-1.
6. Basis of Computation of Incentives: The financial incentives under the scheme shall be calculated in the following manner:
6.1 Eligible Expenditure under Product Design Linked Incentive component: Expenses of approved applicants relating to design, development, testing, fabrication, validation, prototype development, product development, filing of Intellectual Property Rights etc. shall be considered as eligible expenditure for reimbursement under Product Design Linked Incentive component of the scheme. Design and development of EDA Tools shall also be covered under this component of the scheme. The details of eligible expenditure shall be elaborated in the scheme guidelines to be issued by Ministry of Electronics and Information Technology separately.
7. Net Sales Turnover under Deployment Linked Incentive component: Assessment of net sales turnover shall be based on returns filed before relevant taxation authorities and Statutory Auditor certificates.
8. Design Infrastructure: C-DAC (Centre for Development of Advanced Computing), a scientific society, operating under the Ministry of Electronics and Information Technology, will establish the semiconductor design infrastructure under the scheme.
8.1 It shall be entrusted with the responsibility of setting up National EDA tool Grid, repository of IP Cores, hardware and software licenses, patents and trademarks etc and make them available for startups and MSMEs.
8.2 It shall also provide support to startups and MSMEs who seek specific assistance for MPW prototyping for test chip & volume production and testing, validating, prototyping, post silicon validation and other services as deemed appropriate.
8.3 It shall coordinate with similar facilities located across the country and consolidate the semiconductor design expertise for leveraging it under the scheme.
8.4 It shall engage with startups, global technology majors, industry associations, academia, and experts for growth of semiconductor design ecosystem in India and provide policy inputs to Ministry of Electronics and Information Technology.
9. Governance Mechanism
9.1 The scheme will be implemented through C-DAC.
9.2 C-DAC will receive the applications under the scheme and carry out financial and technical appraisal of such applications. It will implement the scheme, submit periodic reports to Ministry of Electronics and Information Technology regarding the progress and performance of the scheme and carry out other responsibilities as assigned by Ministry of Electronics and Information Technology from time to time. The functions and responsibilities of CDAC under this scheme will be elaborated in the Scheme Guidelines to be issued by Ministry of Electronics and Information Technology separately.
9.3 For carrying out activities related to implementation of the Scheme, C-DAC will inter-alia:
9.3.1 Receive the applications, issue acknowledgements, verify eligibility of the applicants for support under the Scheme and issue approvals under the Scheme.
9.3.2 Empanel agency / agencies or consultants as deemed necessary to carry out the technical and financial appraisal of the applications as well as evaluate expertise of the applicants in semiconductor design.
9.3.3 Establish design infrastructure under the scheme either by itself or through other incubator(s) to provide such services to the startups and MSMEs as stated in Para 8 of the Scheme.
9.3.4 Examine claims eligible for disbursement of fiscal support and incentive under the scheme and disburse those as per eligibility.
10. Approval
10.1 The applications received under the scheme will be appraised on an ongoing basis by C-DAC.
10.2 Approval to the selected applicants shall be accorded by the C-DAC and communicated to the applicant under intimation to Ministry of Electronics and Information Technology.
11. Disbursement Process
11.1 The fiscal support against the product development linked incentive component of the scheme shall be released after the approval of the application and achievement of milestones as included in the approval letter.
11.2 Ministry of Electronics and Information Technology shall make budgetary provisions for disbursal of fiscal support and deployment linked incentive to approved projects under the scheme. The disbursement shall be done by CDAC based on approval conditions. CDAC will submit budgetary requirement to Ministry of Electronics and Information Technology as consolidated amount on regular basis and not on project-by-project basis.
11.3 The claims for Deployment Linked Incentive may be submitted after the end of each financial year.
11.4 The detailed procedure for disbursal to applicants will be laid down in the Scheme Guidelines.
12. Impact Assessment: Mid-term appraisal of the scheme will be done after two years of its implementation or as per recommendations of C-DAC to assess the impact of the scheme, offtake by the applicants and economy in terms of the stated objectives. Based on such impact assessment, decision will be taken to increase the tenure of the scheme and change its financial outlay with the approval of the Minister of Electronics and Information Technology.
13. Scheme Guidelines: The Scheme Guidelines shall be issued by Ministry of Electronics and Information Technology (MeitY) separately with the approval of Minister of Electronics and Information Technology.
14. Amendment to Scheme and Guidelines: The scheme and its guidelines shall be reviewed and amended periodically or as per requirement with the approval of Minister of Electronics and Information Technology.
ARVIND KUMAR, Scientist ‘G’ & Group Coordinator
ANNEXURE-1
(Refer paragraph 5.3)
Design Linked Incentive (DLI) Scheme
| Categories of Support | |
| Scheme Component | Description |
| Design Infrastructure Support for Startups / MSMEs | (i) National EDA Grid
(ii) IP Core Repository (iii) Prototyping (iv) Post Silicon Validation |
| Product Design Linked Incentive | Reimbursement of 50% of the eligible expenditure subject to a ceiling of ₹15 Crore incentive per application. |
| Deployment Linked Incentive | Reimbursement of 6% to 4% of net sales over 5 years subject to a ceiling of ₹30 Crore incentive per application. |
